Static And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer Science Essay

Static And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer Science EssayThis paper presents a triple sound off system of logical system web based atmospheric static and dynamic CMOS cascode voltage throw off logic (CVSL) enlistments for improving the functional efficiency and low power consumption. The logic mark strategic is achieved in CVSL by cascading differential pairs of FET devices atomic number 18 capable of processing Boolean functions up to (2N-1) input variables within a whiz roundabout delay. Potentially CVSL is in two ways as dense as primitive NAND/NOR logic, and is compatible with existing design automation tools and relieving the device/process complexity burden for CVSL designs. Significant performance and stringency improvements with simultaneous reduction in power consumption go been investigated employ cadence-90 nm technology. The power requirements for the static and dynamic cascode voltage switch logic circuits are comparedIndex Term s- cascode voltage switch logic (CVSL), Dual plain logic, CMOS VLSI circuit, cadence toolsINTRODUCTIONIn recent years, most of the digital systems are static complementary metal-oxide-semiconductor (CMOS) due to their robust design nature which can implement reliable circuits with ex prison cellent noise margin. However, the demand for luxuriously-performance digital systems requires continuously faster CMOS circuit speed. Dynamic circuits are proven to oblige better circuit performance. But unfortunately, these dynamic design styles suffer from charge sharing, low noise margin, complexity of design, and difficulty in testing. Recently, several researchers throw attempted to use pass-gate logic style to realize static and high performance designs in different digital systems 1-2. Pass-gate logics induce their speed over the traditional static CMOS design due to their high logic functionality and reduction in the number of pFET transistors. However, the degradation of pull-up p erformance for the pass-gate design in the long circuit chain is the major obstacle for most designers to use. Recently, CMOS circuit design technique based cascode voltage switch logic (CVSL) is proposed with legion(predicate) advantages over the conventional static CMOS 3. The domino CMOS, NORA and pseudo-NMOS technique is only effective in non-complementary logic circuits and it cannot apply directly to complementary logic functions. But, CVSL circuits can be applied to complementary logic families. Potential advantages include reduced circuit delay, higher layout immersion, lower power consumption and extended logic flexibility 4.CVSL have been used to implement high-performance arithmetic circuits such as fast multiplications, ROM, RAM as well as pipelined DSP circuits. CVSL is very suitable for asynchronous designs when logic works at that time only the measures are running remaining time is off. This reduces power consumption, especially for large and complex circuits 5. D ual course logic network families are becoming increasingly important for advanced technologies because of the very small amount of charge required to hold a logic state. The cascode-voltage-switch logic supply are evaluated for improved the functional efficiency development 90 nm and 65 nm technology CMOS processes 6.This paper describes dual plain logic network based static and dynamic CMOS cascode voltage switch logic (CVSL) circuits for improving the functional efficiency and power reduction. Significant performance and density improvements with simultaneous reduction in power consumption have been investigated using cadence. The power requirements for the static and dynamic are CVSL compared.design of CMOS CVSL circuitCascode voltage switch logic is a dual-rail logic family. The dual-rail logic based differential CVSL gates are provides the potential of having high fan-in which leads to a reduction in logic depth, high speed, and the capability of generating completion sign als for asynchronous operations.A) Dual rail Logic conceptThe dual rail logic structure is consists of two-pFET are cross-coupled to form a unreserved latch that provides complementary outputs and the latch is driven by an nFET network that can be viewed as two complementary switching functions. The dual rail logic circuits are more complex than single rail logic circuit, but the dual rail circuit can be faster than single rail circuit 6.VDD0 to1 swing0(a) Switching waveform for single rail logicVDD0 to1 swing0(a) Switching waveform for dual rail logicnumber 1 Switching action for single and dual rail networkThe slew rate is simply the rate of flip-flop of the output voltage in time. A large slew rate implies a fast switching speed. In outcome of single rail circuit is generated output, but dual rail logic circuit, both and are generate as output of the gates that is shown in Fig 1. The logic variable is taken to be the difference signalthat effective of slew rate is defines asT his illustrate that dual rail circuit intrinsically exhibits faster switching speed than single rail network. In practical the dual rail logic has some problems increased circuit complexity, increased interconnects required in the layout and timing issues become critical. These problems have been investigated in this static and dynamic differential cascode voltage switch logic circuits.B) Static CVSLStatic differential cascode switch logic circuits usually consist of a push-pull load by pFET and a pair of interrelated (requiring both true and complement signals) binary decision trees by nFET. The Differential CVSL tree is properly intentional into two ways, such that(1) When the input vector is the true of the switching function, that node is disconnected from ground and node is connected to ground by a uncomparable conducting path through the tree.(2) When the input vector is false of, the reverse holds.The logic trees may be further minimized from the full differential form usin g logic minimization algorithms. This version, which might be termed a static CVSL gate, is lower than a conventional complementary gate employing a p-tree and n-tree. This because switching action, the p pull-ups have to fight the n pull-down trees.VDDpFET LatchpFET2pFET1nFET Logic ArrayFig 3 Static CMOS CVSL gate circuitA design procedure for differential CVSL circuits using the pictorial nature of the Karnaugh map is proposed. A CMOS cell designed with this procedure is compared with the corresponding gate logic design. A CVSL circuit of the Boolean function is habituated by that is shown in Fig 2. Note that only 12 transistors are required for this differential CVSL circuit design, two p-transistors and ten n-transistors instead of 10 p-transistors and 10 n-transistors using a NAND-NAND configuration or conventional gate logic design. The transistor pFET latching circuit is consists of two stable states. The conductions of the source-gate voltage on the devices are granted asT he behavior of the latches is that and is andare voltage complements in this circuit, so one is high while other is low. The latching is induced by nFET switching network, which biases pFET1 into conduction from that timeWith pFET1 conducting, locomotes to, which drives pFET2 into crosscut from that timeThis represents one stable state of the latch. The voltage is pulled to, which gives and biases pFET2 into conduction and pFET1 into cutoff. From this principle, there is no direct path for flow rate flow from to ground for either situation, so that only leakage currents exist.C) Dynamic CVSLThe static CVSL logic gate can be transformed into dynamic circuit by rewiring the pFET latch to the measure-driven arrangement, shown in Fig 3. This eliminates the feedback loop and changes the two-pFET into precharge devices that are controlled by the clock. When the value of clock is zero, drives both pFET into conduction mode that result is precharging of the output nodes. To avoid DC-cur rent flow during this event, an evaluation nFET is controlled by the clock, so it is OFF during the precharge time.VDDnFETCombinational networkDifferentialInputsClockClock (precharge)pFET1pFET2Fig 3 Basic structure of a dynamic CVSL gate circuitThe precharge clock is zero at event, which allows the voltages across both and to precharge to value ofWhen the clock change to the value is one, the circuit is driven into the evaluation phase. nFET is ON and the input signals are valid. For the case true signals switch is open and is held high while complementary switch is closed and discharges toThe output voltages are initially complementary. However, the left output voltage is face to the usual dynamic problems of charge sharing and charge leakage, which reduces its value in time. As with all dynamic logic circuits, this gives rise to a minimum clock frequency. The pFET charge is controlled by the output states and. This dynamic cascade switch logic circuit allows with small aspect rat io for charge compensation without excessive current flowing onto the node.Simulation result and analysisThe performance of the static and dynamic cascode voltage switch logic circuits designed and evaluated through cadence-gpdk90 nm technology.The static CMOS cell designed CVSL circuit of the Boolean function is given by. The differential input signals A, B, C, D, and E and also complementary input signals are applied to the pull-down (nFET network) network of the circuit. The fugitive response voltage is set as 1 V with 0.1 ns rise/fall time. The cross-coupled latch is provides complementary outputs and that is shown in Fig 4ABCDEQFig 4 Simulation waveforms for static CVSL circuitClockABCDQFig 5 Simulation waveforms for dynamic CVSL circuitThe dynamic CMOS cell designed CVSL circuit of the Boolean function is given byas a four XOR gate implementation. This is just two-domino gates operating on true and complement inputs with a minimized logic tree. The transient response voltage is set as 1 V with 0.1 ns rise/fall time. The cross-coupled latch is provides complementary outputs and that is shown in Fig 5The static and dynamic CVSL circuits power consumption is calculated and given in table 1Table 1 Static and dynamic CVSL Power consumptionCMOS LogicPower consumptionStatic CVSL166 uWDynamic CVSL224 uWConclusionsThis paper implements a dual rail logic circuit design technique for CMOS differential cascade voltage switch circuits. This CVSL gates facilitates that improving the functional efficiency and low power consumption. The static and dynamic CMOS differential CVSL circuits have been investigated using cadence-gpdk90 nm technology.